The present invention relates generally to a semiconductor device having a field-effect transistor (FET) structure. More particularly, the invention relates to an FET, such as a GaAs FET designed for ultra-high frequency operation.
In recent years, satellite broadcasting systems have become increasingly available. In such satellite broadcasting systems, high-quality data, such as image data, pulse-code-modulated signals, and so forth, are broadcast at ultra-high frequencies, e.g. at about 12 GHz. Thus, receiving systems for satellite broadcasting systems have increased the demand for low-noise, ultra-high-frequency FET's.
The ultra-high-frequency FET, such as a GaAs FET can be represented by the equivalent circuit shown in FIG. 1. The noise figure F.sub.0 of an FET can be described by the following equation: ##EQU1##
where K.sub.f is a unique constant for each individual device, the so-called "fitting factor";
C.sub.gs is the gate-source capacitance (=input capacitance)
R.sub.g is the gate resistance at high frequencies;
R.sub.s is the source resistance; and
gm is the transmission conductance of the FET.
One way to reduce the noise figure F.sub.0 is to reduce the gate resistance R.sub.g. The gate resistance R.sub.g can be expressed by the following equation: ##EQU2##
where .pi..sub.g is the resistivity of the gate metal;
S is the cross-sectional area of the gate;
Z.sub.u is the unit gate width, and
Z.sub.t is the total gate width.
As shown in FIGS. 2(A) to 2(C), the unit gate width Z.sub.u can be reduced by increasing the number of supply points P relative to the total gate width Z.sub.t. For instance, as shown in FIG. 2(A), when one supply point P is active in the gate electrode 1, the unit gate width Z.sub.u becomes 1/2Z.sub.t. When two supply points P are active, the unit gate width Z.sub.u 1/4Z.sub.t, as shown in FIG. 2(B). By further increasing the number of supply points to three as shown in FIG. 2(C), the unit gate width Z.sub.u become 1/6Z.sub.t.
As will be appreciated herefrom, in general, if N supply points are built into the gate electrode 1, the unit gate width Z.sub.u will be Z.sub.u =Z.sub.t /2N. Since the gate resistance R.sub.g varies in proportion to the square of the unit gate width Z.sub.u, when two supply points are active, the gate resistance R.sub.g the gate electrode 1 will be 1/4 of that when a single supply point P is available. Similarly, when three supply points P are provided for the gate electrode 1, the gate resistance R.sub.g will be 1/9 of that when a single supply point is used.
In summary, increasing the number of supply points P in the gate electrode reduces the gate resistance R.sub.g and thus the noise figure F.sub.0 significantly.
On the other hand, in order to increase the number of supply points P in the gate electrode 1, an increased number of electrodes, so-called bonding pads, are required to supply the gate potential for the corresponding supply points P. This results in expansion of the gate cell area, resulting in a larger chip overall. For instance, as shown in FIGS. 3(A) to 3(C), a semiconductor device with an FET structure has a source region 2 and a drain region 3 on opposite sides of the gate electrode 1. The bonding pads 4 are installed on the source region side in order to prevent undue increase in the gate-drain capacitance C.sub.dg. The bonding pads 4 are surrounded by the source region 2 for the sake of shielding. Sine it has been considered essential to shield the bonding pads 4 by surrounding them with the source region metallization, it has been considered inevitable that the total length of the source region 2 will increase as the number of bonding pads 4 increases.
Therefore, as shown FIGS. 3(A) to 3(C), when two bonding pads 4 are connected to two supply points P on the gate electrode 1, as shown in FIG. 3(B), the required total length W.sub.2 is greater than that length W.sub.1 required for a single bonding pad for a single supply point. Similarly, when three bonding pads 4 is provided for three supply points, the total length W.sub.3 of the source region 2 is even greater than that length W.sub.2 for two bonding pads. In summary, increasing the number of supply points P in the gate electrode 1 thus results in an increase in the number of bonding pads 4 and in the total length W of the source region. This implies expansion of the gate cell dimensions and thus of the chip overall. Therefore, the finished GaAs FET becomes more expensive due to the increased cost of materials and so forth. In addition, expanding the chip size lowers the production yield of the semiconductor chip and of course expansion of the chip size is considered unfavorable in itself.
As far as the chip area alone is concerned, these problems can be resolved by using a multi-level structure for the semiconductor device. In the multi-level integration structure, the bonding pads 4 need not multiply as the number of supply points P in the gate electrode 1 increases. On the other hand, in the multi-level structure, it is necessary to deposit additional insulating layers by way of the CVD process or the like in order to limit the gate-source capacitance (input capacitance). Furthermore, it is also necessary to form through openings through the insulating layers to allow contacts to establish electrical connections. This results in relatively high production costs.